Part Number Hot Search : 
05D12 PE44401 KSD201 0D102 MJE15032 STBB56I K2617 Z1000
Product Description
Full Text Search
 

To Download SAF-TC1920-LEBBA Datasheet File
  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
　
 

  Datasheet File OCR Text:
  never stop thinking. microcontrollers data sheet, v 1.3, oct. 2003 tc1920 32-bit single-chip microcontroller
edition 2003-10 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2003. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
microcontrollers data sheet, v 1.3, oct. 2003 never stop thinking. tc1920 32-bit single-chip microcontroller
tc1920 preliminary revision history: 2003-10 v1.3 previous version: 1.2 page subjects (major changes since last revision) asc and ssc baudrates calculated for 50 mhz dc parameters updated with characterization values ac parameters updated with characterization values we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
tc1920 preliminary data sheet 1 v 1.3, 2003-10 tc1920 features the tc1920 offers a 32 bit tricore based microcontroller/dsp, which is mainly designed for automotive telematics applications. due to its high integration, this microcontroller/ dsp offers high system performance at minimized cost. typical telematics functions processed by risc-, dsp- and speech- (codec) modules are now combined in one component. the combination of dedicated automotive peripherals (can, j1850) and standard peripherals (adc, ssc/spi, asc and iic), makes this microcontroller/dsp the engine tailored for a wide variety of telematics applications such as navigation, emergency call, speech interface or communication interface. ? tricore cpu/dsp with 4-stage pipeline: ? 100 mhz max. cpu clock frequency, 50 mhz max. fpi bus clock frequency. ? 32-bit super-scalar tricore main cpu ? 4-gbyte unified memory space support ? fast context-switching ? dual 16 x 16 multiply-accumulate (mac) unit ? 64-bit local memory bus (lmb) ? 32-bit flexible peripheral interface (fpi) ? 32-bit wide external bus unit (ebu)  32-bit peripheral control processor (pcp2) with dma-support  on-chip memories: ? 24 kbyte code scratch-pad ram (csram) ? 8 kbyte instruction cache (icache) ? 24 kbyte data scratch-pad ram (dsram) ? 8 kbyte data cache (dcache) ? 64 kbyte fast lmb sram ? 16 kbyte fpi sram (of which 8 kbyte stand-by sram) ? 20 kbyte pcp ram: 16 kbyte code and 4 kbyte data sram ? 32 kbyte boot rom  product specific peripherals: ? 14-bit double codec with flexible sample rates and fifo support  automotive peripherals: ? two independent can-nodes (twincan) with gateway support ? j1850 (sdlm)  standard peripherals: ? 6-channel, 8-/10-/12-bit adc ? 3 x asynchronous serial interface (asc) with irda-support ? 1 spi-compatible synchronous serial interface ? 2-channel iic ? 6 x 32 bit timer ? 16 i/o- and interrupt pins (gpio)  general peripherals: ? real time clock (rtc)
tc1920 data sheet 2 v 1.3, 2003-10 preliminary ? watchdog timer (wdt)  clock generation unit with pll  debug support: ? debug interface (ocds level 2) with trace port  power saving features  dual voltage supply (1.8v core, 3.3v i/o)  -40c to +85c temperature range  lbga-260 package
tc1920 preliminary data sheet 3 v 1.3, 2003-10 block diagram the figure below shows the block diagram of the tc1920 device. figure 1 tc1920 device block diagram dmu 24kb dsram 8kb dcache 32-bit flexible peripheral interface (fpi)bus tc1920 boot rom 32kb sram 16kb rtc stm scu j1850 asc0 adc asc1 codec asc2 gptu0 ssc gptu1 iic port control ocds debug interface /jtag twin can 64-bit local memory bus (lmb) ebu lfi bridge sram 64 kb tricore (tc1.3) cps pmu 24kb csram 8kb icache mmu 32 bit external memory bus fpi-bus interface pcp2 pcode 16kb pram 4kb
tc1920 data sheet 4 v 1.3, 2003-10 preliminary target applications  on-board and off-board navigation  emergency call systems  car speech interface  car communication interface  gateways: automotive - infotainment  occupant sensing  drowsiness detection  rear- & side-mirror replacement  pre-crash sensing logical symbol figure 2 logical symbol of the tc1920 device tc1920 g p io / gptu1 alternate functions bypass xtal1 xtal2 xtal3 clkout xtal4 pll_ctrl v dd v ss v ddp v ddsb v dda v ddpll v sspll v ddosc1 v ssosc1 port 1 8-bit port 0 8-bit port 2 16-bit port 3 16-bit 8 ocds/jtag control codec analog power supply v dd_cod0 adc analog power supply nmi hdrst porst d igital c irc uitry power supply oscillators pll general control test v ddosc2 v ssosc2 g p io /ex ix, codec bypass can0/1 / j1850 / ssc a sc 0 / iic a sc 1/2 / ad c m u x ad c e xt in / g pt u 0 v ssa v aref v agnd v ss_cod0 v dd_cod1 v ss_cod1 v ref_cod v gnd_cod gpio / trace codec 0/1 10 adc 6 external bus interface 83 port 5 16
tc1920 preliminary data sheet 5 v 1.3, 2003-10 pin configuration figure 3 tc1920 pinning lbga 260 a b c d f g h j k l m n p r t u v e a b c d e f g h j k l m n p r t u v 123456789101112131415161718 123456789101112131415161718 v ssp _osc v ss _ osc v ddr ad31 ebu clk bfclk 0 rd rd/ wr ale cs1 cs2 cs3 v ddp p5.9 brk out ocd se p0.2 p0.5 p0.1 p1.2 tdo p3.8 p0.3 p1.1 p3.15 p3.11 p3.10 p3.9 p3.13 p0.6 p3.14 p3.6 p2.2 tck p2.0 p2.6 p3.5 p3.0 p2.9 p2.1 p2.7 p2.3 p2.12 p2.15 p2.4 p2.14 v ddp_ cod0 p2.8 p2.10 p2.13 p2.11 clk out ao1+ v ssa_ cod0 by pass ai1+ v gnd _ cod cext ao- code c_dis ai0+ v ssp_ cod0 v ref _ cod ao1- p4.0 ao+ p4.4 v ssp _ adc ai1- v dd _ guard ai0- p4.2 v ssp _ osc v ss _ pll p4.1 v ssa _ adc pllctrl _a0 v ddp_ osc p4.3 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ddp v ddp v ddp v ddp v ddp v ddp v ddp v ddp v ddp v ddp v ddp v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v dd v dd v ddr ad27 ad30 ad26 ad28 ad23 ad24 ad25 ad18 ad19 ad20 ad22 ad21 ad13 ad14 ad15 ad17 ad10 ad11 ad12 ad16 ad6 ad5 ad2 ad3 ad29 ad8 ad9 ad7 ad4 ad1 ad0 a22 a20 a21 a15 a18 a23 a19 a11 a14 a17 a8 a13 a16 a3 a5 a7 a0 a2 a9 a10 a4 a6 a12 a1 bc1 bc2 ras cas bc3 cs5 cs4 bc0 cs6 cs emu wait baa cs0 cm delay cs ovl cs glb adv mr/w cke p5.12 p5.14 p5.15 p5.8 p5.7 p5.11 p5.13 p5.5 p5.2 p5.6 p5.10 p5.3 p5.1 p5.4 p5.0 brkin tms v dd_ sb p1.5 p1.3 trst tdi p0.0 p1.6 p1.4 p1.0 p1.7 p0.4 p3.2 p3.3 p3.1 p0.7 scan mode p3.7 p3.12 p3.4 p2.5 nmi pors t hrst v ssp _ adc v ddp _ adc v ssp _ adc v agnd _ adc v aref _ adc p4.5 v dd _ pll v ss _ guard v ss _ guard v dd _ osc1 xtal2 v ddp_ osc xtal1 v dd_ osc2 xtal4 xtal3 tm_ ctrl0 tm_ ctrl1 v ss v ss v ss v ss top view
tc1920 data sheet 6 v 1.3, 2003-10 preliminary pin list table 1 pin definitions and functions symbol pad 1) bga ball in/ out 2) functions ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 274 273 272 271 270 269 268 264 263 262 261 260 259 258 253 252 251 250 249 248 247 243 242 241 240 239 238 237 232 231 230 229 l3 l2 k3 k4 l1 k2 k1 j3 j1 j2 h1 h2 h3 g1 g2 g3 h4 g4 e4 f1 f2 f4 f3 e1 e2 e3 d1 c1 d2 d3 c2 b1 i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s external bus unit interface external address/data bus (multiplexed bus mode) or data bus (demultiplexed bus mode) for the ebu: address/data bus / data bus line 0 address/data bus / data bus line 1 address/data bus / data bus line 2 address/data bus / data bus line 3 address/data bus / data bus line 4 address/data bus / data bus line 5 address/data bus / data bus line 6 address/data bus / data bus line 7 address/data bus / data bus line 8 address/data bus / data bus line 9 address/data bus / data bus line 10 address/data bus / data bus line 11 address/data bus / data bus line 12 address/data bus / data bus line 13 address/data bus / data bus line 14 address/data bus / data bus line 15 address/data bus / data bus line 16 address/data bus / data bus line 17 address/data bus / data bus line 18 address/data bus / data bus line 19 address/data bus / data bus line 20 address/data bus / data bus line 21 address/data bus / data bus line 22 address/data bus / data bus line 23 address/data bus / data bus line 24 address/data bus / data bus line 25 address/data bus / data bus line 26 address/data bus / data bus line 27 address/data bus / data bus line 28 address/data bus / data bus line 29 address/data bus / data bus line 30 address/data bus / data bus line 31
tc1920 preliminary data sheet 7 v 1.3, 2003-10 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 cs0 cs1 cs2 cs3 cs4 cs5 cs6 csemu csovl 9 6 5 4 3 2 307 306 303 302 301 300 299 295 294 293 292 291 290 289 285 284 283 282 28 27 26 25 24 23 22 36 37 v2 t5 v1 u3 t4 u2 t3 u1 r3 t2 t1 p3 r5 r2 p2 n3 r1 p1 n2 p4 m3 n4 m4 n1 r9 r8 r7 v7 v6 v5 u7 v8 t9 i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s i/o,s o,u o,u o,u o,u o,u o,u o,u o,u o,u external bus unit interface (continued) external address bus for the ebu or chip select output lines. address bus line 0 address bus line 1 address bus line 2 address bus line 3 address bus line 4 address bus line 5 address bus line 6 address bus line 7 address bus line 8 address bus line 9 address bus line 10 address bus line 11 address bus line 12 address bus line 13 address bus line 14 address bus line 15 address bus line 16 address bus line 17 address bus line 18 address bus line 19 address bus line 20 address bus line 21 address bus line 22 address bus line 23 chip select output 0 chip select output 1 chip select output 2 chip select output 3 chip select output 4 chip select output 5 chip select output 6 chip select for emulator region chip select for emulator overlay memory table 1 pin definitions and functions symbol pad 1) bga ball in/ out 2) functions
tc1920 data sheet 8 v 1.3, 2003-10 preliminary rd rd/wr ale adv bc0 bc1 bc2 bc3 wait baa ebuclk bfclk0 csglb cmdelay mr/w cke ras cas 11 12 45 46 218 17 16 15 32 33 278 279 38 39 40 44 13 14 u4 v3 t10 r10 t7 r6 v4 u6 t8 u8 m1 m2 u9 v9 v10 u10 u5 t6 i/o,u i/o,u o,d o,u i/o,u i/o,u i/o,u i/o,u i/o,u o,u o,d o,d o,u i,u o,u o,d o,u o,u external bus unit interface (continued) control bus for the ebu control lines. read control line write control line address latch enable address valid output byte control line 0 byte control line 1 byte control line 2 byte control line 3 wait input burst address advance output external bus clock additional clock chip select global command delay motorola-style read/write clock enable row address strobe column address strobe p0 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 94 95 98 102 103 104 105 106 r18 n16 n17 p15 p18 n18 n15 m15 i/o i/o i/o i/o i/o i/o i/o i/o port 0 port 0 serves as 8-bi t general purpose i/o port, that can also be used for the codec digital signals. p0.[3:0] also serve as external interrupt inputs. exi0in external interrupt input 0 exi1in ext. interrupt input 1 / data_in exi2in ext. interrupt input 2 / data_out exi3in ext. interrupt input 3 / mclk sclk lrck mute0 mute1 table 1 pin definitions and functions symbol pad 1) bga ball in/ out 2) functions
tc1920 preliminary data sheet 9 v 1.3, 2003-10 p1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 83 84 85 86 87 91 92 93 v18 r16 p16 t17 u18 r17 t18 p17 i/o i/o i/o i/o i/o i/o i/o i/o port 1 port 1 is an 8-bit bidirectional general purpose i/o port which is also used as input/output for the gptu1 gptu1.0 gptu1 i/o line 0 gptu1.1 gptu1 i/o line 1 gptu1.2 gptu1 i/o line 2 gptu1.3 gptu1 i/o line 3 gptu1.4 gptu1 i/o line 4 gptu1.5 gptu1 i/o line 5 gptu1.6 gptu1 i/o line 6 gptu1.7 gptu1 i/o line 7 p2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 131 132 133 137 138 139 140 141 142 143 147 148 149 150 151 152 g18 g17 h16 f18 e18 f17 h15 g16 e17 g15 d18 c18 f16 d17 e16 f15 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 2 port 2 is a 16-bit bidirectional general purpose i/o port which is also used as input/output for serial interfaces (can, j1850, iic, asc0, ssc) rxdcan0 can 0 receiver input txdcan0 can 0 transmitter output rxdcan1 can 1 receiver input txdcan1 can 1 transmitter output rxj1850 sdlm receiver input txj1850 sdlm transmitter output scl0 iic serial port clock line 0 sda0 iic serial port data line 0 scl1 iic serial port clock line 1 sda1 iic serial port data line 1 rxd0 asc0 receiver input/output txd0 asc0 transmitter output sclk ssc clock line mrst ssc master receive/slave transmit mtsr ssc master transmit/slave receive pll_clc.lock monitoring of pll_clc.lock table 1 pin definitions and functions symbol pad 1) bga ball in/ out 2) functions
tc1920 data sheet 10 v 1.3, 2003-10 preliminary p3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 p3.14 p3.15 107 108 109 110 115 116 117 118 119 120 124 125 126 127 128 129 l15 m16 m17 m18 l17 l16 l18 k17 k18 j18 k16 j17 j15 h18 h17 j16 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 3 port 3 is a 16-bit bidirectional general purpose i/o port which is also used as input/output for serial interfaces (asc0 and asc1), for timer (gptu0) and adc control lines gptu0.0 gptu0 i/o line 0 gptu0.1 gptu0 i/o line 1 gptu0.2 gptu0 i/o line 2 gptu0.3 gptu0 i/o line 3 gptu0.4 gptu0 i/o line 4 gptu0.5 gptu0 i/o line 5 gptu0.6 gptu0 i/o line 6 gptu0.7 gptu0 i/o line 7 rxd1 asc1 receiver input/output txd1 asc1 transmitter output rxd2 asc2 receiver input/output txd2 asc2 transmitter output oscbyp latch-in input adcmux0/exi5in/hwcfg0 adc external mux control 0 / external interrupt input 5 / hardware configuration input 0 / adcmux1/exi6in/hwcfg1 adc external mux control 1 / external interrupt input 6 / hardware configuration input 1 adcmux2/exi7in/hwcfg2 adc external mux control 2 / external interrupt input 7/ hardware configuration input 2 adextin adc external trigger input table 1 pin definitions and functions symbol pad 1) bga ball in/ out 2) functions
tc1920 preliminary data sheet 11 v 1.3, 2003-10 p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 190 191 192 193 194 195 c11 a11 b10 a10 c10 a9 i i i i i i port 4 port 4 provides the 6 analog input lines for the ad converter (adc). ain0 analog input 0 ain1 analog input 1 ain2 analog input 2 ain3 analog input 3 ain4 analog input 4 ain5 analog input 5 codec ai0+ ai0- ao0+ ao0- ai1+ ai1- ao1+ ao1- cext codec_dis 180 181 169 165 176 177 170 172 162 163 d13 a13 a15 b15 d14 a14 c14 b14 a17 c16 i i o o i i o o i i codec codec 0 non-inverting input codec 0 inverting input codec 0 non-inverting output codec 0 inverting output codec 1 non-inverting input codec 1 inverting input codec 1 non-inverting output codec 1 inverting output codec external clock input codec disable (power saving) debug trst tck tdi tdo 3) tms ocdse brkin brkout 3) 82 81 80 76 75 73 72 71 u17 t16 v17 u16 t15 v16 u15 t14 i,d i,u i,u o i,u i,u i,u o debug (ocds/jtag control) reset/module enable jtag clock input serial data input serial data output state machine control signal ocds enable input ocds break input ocds break output test scan_mode pllctrl_ao tm_ctrl0 tm_ctrl1 114 202 215 216 k15 b8 b4 a3 i i i i test pins scan mode control current of different analog stages test mode control 0 test mode control 1 table 1 pin definitions and functions symbol pad 1) bga ball in/ out 2) functions
tc1920 data sheet 12 v 1.3, 2003-10 preliminary p5 trace [15:0] p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 p5.8 p5.9 p5.10 p5.11 p5.12 p5.13 p5.14 p5.15 70 69 68 67 63 62 61 60 59 58 54 53 52 51 48 47 v15 u14 t13 r14 v14 r13 u13 t12 r12 r11 v13 u12 t11 v12 u11 v11 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 5 trace lines to output cpu or pcp2 ocds level 2 trace signals cpu or pcp2 trace output 0 / gpio cpu or pcp2 trace output 1 / gpio cpu or pcp2 trace output 2 / gpio cpu or pcp2 trace output 3 / gpio cpu or pcp2 trace output 4 / gpio cpu or pcp2 trace output 5 / gpio cpu or pcp2 trace output 6 / gpio cpu or pcp2 trace output 7 / gpio cpu or pcp2 trace output 8 / gpio cpu or pcp2 trace output 9 / gpio cpu or pcp2 trace output 10 / gpio cpu or pcp2 trace output 11 / gpio cpu or pcp2 trace output 12 / gpio cpu or pcp2 trace output 13 / gpio cpu or pcp2 trace output 14 / gpio cpu or pcp2 trace output 15 / gpio bypass 161 b17 i,d pll bypass control input. nmi 160 a18 i,u non-maskable interrupt input hrst 159 d16 i/o,u bidirectional hardware reset porst 158 b18 i,u power-on reset input porst must be active during power-up of the device clkout 156 c17 o cpu clock output xtal1 xtal2 208 207 a6 b7 i o pll/oscillator input/output xtal3 xtal4 214 213 a4 b5 i o real time clock oscillator input/output (32 khz) v dd_osc1 206 a7 - main oscillator power supply (1.8v) v dd_osc2 212 c6 - rtc oscillator power supply (1.8v) v ss_osc 211 b6 - rtc & main oscillator ground (1.8v) v ddp_osc 205 d7 - rtc & main oscillator power supply (3.3v) table 1 pin definitions and functions symbol pad 1) bga ball in/ out 2) functions
tc1920 preliminary data sheet 13 v 1.3, 2003-10 v ddp_osc 210 c7 - rtc & main oscillator power supply (3.3v) v ssp_osc 203 d8 - rtc & main oscillator ground (3.3v) v ssp_osc 209 a5 - rtc & main oscillator ground (3.3v) v dd_pll 198 d9 - pll supply (1.8v) v ss_pll 199 b9 - pll ground (1.8v) v ddp_adc 185 c12 - adc port and analog part power supply (3.3v) v ssp_adc 184 b12 - adc port and analog part ground (3.3v) v ssp_adc 186 d12 - adc port and analog part ground (3.3v) v ssp_adc 196 d10 - adc port and analog part ground (3.3v) v ssa_adc 187 a12 - adc analog ground (3.3v) v aref_adc 189 d11 - adc reference voltage v agnd_adc 188 b11 - adc reference ground v ddp_cod0 166 e15 - codec 0 port and analog part power supply (3.3v) v ssa_cod0 167 d15 - codec 0 analog ground v ddp_cod1 175 e15 - codec 1 port and analog part power supply (3.3v) v ssa_cod1 174 d15 - codec 1 analog ground v ssp_cod0 168 c15 - codec 0 pad ground (3.3v) v ssp_cod1 173 c15 codec 1 pad ground (3.3v) v ref_cod 178 b13 - codec 0,1 reference voltage v gnd_cod 179 c13 - codec 0,1 reference ground v ddr 217 a2 - stand-by sram power supply (1.8v) v ddr 224 c5 - stand-by sram power supply (1.8v) v dd_guard 200 c9 - guard ring supply (1.8v) v ss_guard 201 a8 - guard ring ground (1.8v) v ss_guard 204 c8 - guard ring ground (1.8v) v dd_sb 97 r15 - stand-by sram battery backed stand-by power supply (1.8v) v ddp 4) - port pins power supply (3.3v) table 1 pin definitions and functions symbol pad 1) bga ball in/ out 2) functions
tc1920 data sheet 14 v 1.3, 2003-10 preliminary v dd 5) - core power supply (1.8v) v ss 6) - ground for core and ports 1) the pin number describes the position of a signal on the silicon. the mapping of the pin number to the corresponding bga ball is done according to the used package. 2) the notification ?,u? after the input/output type defines an internal pull-up resistor. an internal pull-down resistor is indicated by ?,d?. for the lines ad[31:0] and a[23 :0], the type of the pull device can be selected ?s?. 3) output driver comparable to gpio medium driver/sharp edge. 4) the bga balls for the 3.3v port power supply are: g11, g12, g7, g8, h12, h7, l12, l7, m11, m12, m7, m8. 5) the bga balls for the 1.8v core power supply are: a16, b16, b3, c4, d5, j4, l4, r4. 6) the bga balls for the digital ground are: a1, b2, c3, d4, d6, g10, g9, h10, h11, h8, h9, j10, j11, j12, j7, j8, j9, k10, k11, k12, k7, k8, k9, l10, l11, l8, l9, m10, m9. table 1 pin definitions and functions symbol pad 1) bga ball in/ out 2) functions
tc1920 preliminary data sheet 15 v 1.3, 2003-10 system architecture and control 32-bit tricore cpu  32-bit architecture with 4-gbyte unified data, program and input/output address space  fast automatic context-switch  dual 16 x 16 multiply-accumulate (mac) unit  saturating integer arithmetic  register based design with multiple variable register banks  bit handling  packed data operations  zero overhead loop  precise exceptions  flexible power management instruction set with high efficiency:  16/32-bit instructions for reduced code size  little endian byte ordering with support for big and little endian byte ordering at bus interface  boolean, array of bits, character, signed and unsigned integer, integer with saturation, signed fraction, double word integers and ieee-754 single precision floating-point data types  bit, 8-bit byte, 16-bit half word, 32-bit word and 64-bit double word data formats  powerful instruction set  flexible and efficient addressing mode for high code density on-chip code memories pmu scratch-pad sram (csram): the pmu memory consists of 24-kbyte code scratchpad ram (csram) and 8-kbyte instruction cache (icache). address range of the csram:  d400 0000 h - d400 5fff h boot rom (brom): the tc1920 contains 32 kbyte of boot ro m memory, which can be used for device operating mode initialization routines, bootstrap loader support or test functions. the address range of the boot rom is:  dfff 8000 h ? dfff ffff h
tc1920 data sheet 16 v 1.3, 2003-10 preliminary on-chip data memories dmu scratch-pad sram (dsram): the dmu memory consists of 24-kbyte data scratchpad ram (dsram) and 8-kbyte data cache (dcache). address range of the dsram:  d000 0000 h - d000 5fff h local memory bus memory (lmbram): address range of the 64 kbyte local memory bus memory:  c000 0000 h - c000 ffff h (in segment 12 for cached operation)  e800 0000 h - e800 ffff h (in segment 14 for non-cached operation) fpi-bus data memory (fpidram): the fpi-bus data memory (fpidram) is a 16-kbyte static ram located on the fpi- bus. it contains two parts: fpidram0 and fpidram1. one half of it (fpidram1) can be used for standby power operation. address range of the fpi data memory:  9fff 8000 h - 9fff bfff h (in segment 9 for cached operation)  bfff 8000 h - bfff bfff h (in segment 11 for non-cached operation) on-chip pcp memories pcp code memory (pcode): the address range of the 16 kbyte pcp code memory (pcode) is:  f002 0000 h - f002 3fff h pcp data memory (pram): the address range of the 4 kbyte pcp data memory (pram) is:  f001 0000 h - f001 0fff h
tc1920 preliminary data sheet 17 v 1.3, 2003-10 system control unit (scu) the system control unit of the tc1920 basically handles all system control tasks. all these system functions are tightly coupled and therefore they are handled physically by one unit, the scu. the system tasks of the scu are:  clock generation and control  reset control  power management control and wake-up  watchdog timer  trace port control  device identification  standby sram control  external interrupt capability (8 sources) system timer (stm) the system timer is designed for global system timing applications requiring both high precision and long range. it is used by the cpu for softw are operating system issues. features:  free-running 56-bit counter  all 56 bits can be read synchronously  different 32-bit portions of the 56-bit counter can be read synchronously  driven by clock, f stm (normally identical with the system clock).  counting begins at power-on reset  continuous operation is not affected by any reset condition except power-on reset
tc1920 data sheet 18 v 1.3, 2003-10 preliminary external bus interface (ebu_lmb) ebu_lmb is connected to the local memory bus (lmb) of the tc1920 and also to the fpi bus. ebu_lmb is always a slave on the lmb and a master/slave on the fpi bus. any lmb masters thus can access external memories or devices through ebu_lmb. currently the maximum length of the bursts are according to the size of program and data cache lines, i.e. 8 x 32-bit words. single transfers (non-burst) are supported for 8- bit, 16-bit and 32-bit wide access. figure 4 ebu_lmb block diagram features supported in ebu_lmb:  local memory bus (lmb 64-bit) support.  external bus frequency: lmb frequency = 1:1 or 1:2 or 1:4.  highly programmable access parameters.  intel-style and motorola-sty le peripheral/device support.  sdram support (burst access, multibanking, precharge, refresh).  16- and 32-bit sdram data bus and support of 64, 128 and 256mbit devices.  burst flash support.  multiplexed access (address & data on the same bus) when sdram is not present on the external bus.  data buffering: code prefetch buffer, read/write buffer.  external master arbitration (compatible to c166 and other tricore devices).  8 programmable address regions (1 dedicated for emulator).  little-endian and big-endian support. cs glb signal, dedicated pin, bit programmable to combine one or more cs lines, for buffer control. rmw signal reflecting a read-modify-write action.  signal for controlling data fl ow of slow-memory buffer.  slave unit for external (off-chip) master to access devices on the fpi bus.  master unit for fpi master to access external (off-chip) devices.  data mover engine. sdram buffer xbc ebu_lmb xmi fpi bus 32-bit external bus 32-bit lmb bus 64-bit dme ebul3045_l external bus unit external master slower devices 50 mhz
tc1920 preliminary data sheet 19 v 1.3, 2003-10 interrupt system  flexible interrupt prioritizing scheme with 256 interrupt priority levels  fast interrupt response  service requests are serviced by the cpu or by the pcp (two independent interrupt buses, that can be selected by each interrupt source) figure 5 block diagram interrupt system module c n service request nodes module a n service request nodes module b n service request nodes 12 service request nodes 12 pcp interrupt arbitration bus c pu interrupt arbitration bus pcp interrupt control unit (picu) pcp kernel pcp interrupt control 4 service request nodes 4 cpu interrupt control unit (icu) cpu core m ain interrupt control module kernel module kernel module kernel
tc1920 data sheet 20 v 1.3, 2003-10 preliminary peripheral control processor (pcp) figure 6 pcp block diagram the pcp is designed to work in partnership with a host cpu and performs many of the tasks that would conventionally be performed by cpu interrupt service routines or a dma controller. the pcp off-loads the host cpu from most of the time critical interrupts, easing the implementation of systems based on operating systems. in principle the pcp may be considered to be a conventional processor which only executes code in response to interrupt se rvice requests (i.e. has no processing which is not at interrupt level). it has an architecture which efficiently supports dma type of bus transactions to / from arbitrary devices and memory addresses and also some reasonable computational capabilities. whenever the pcp responds to a pcp interrupt request (which has a specific interrupt priority level) it will use a register set ("context") specific to that individual interrupt level and will also generally execute code which is also specific to that interrupt level. for this reason the term "channel" will be used throughout the remainder of this document to refer to all pcp resources associated with a particular pcp interrupt level. the architecture is flexible enough to allow the implementation of a subset of the commands/instructions as a simple dma controller. the pcp has a harvard architecture (i.e. separate code and data me mory spaces). any fpi bus master (including the pcp itself) can access both pcp code (pcode) and data (pram) memory via the fpi bus. mcb04784_mod pcp processor core pcp service req. nodes psrns pcp interrupt c ontrol unit picu parameter memory pram code memory pcode fp i-interface pcp interrupt arbitration bus cp u interrupt arbitration bus fpi bus
tc1920 preliminary data sheet 21 v 1.3, 2003-10 fpi bus the flexible peripheral interconnect bus is designed with the requirements of high- performance systems-on-chip in mind. key features:  core independent  multi-master capability  demultiplexed operation  clock synchronous  peak transfer rate of up to 200 mbytes/s (@ 50 mhz bus clock)  address and data bus scalable (32 bit address bus, 32 bit data bus )  8-/16- and 32 bit data transfers  broad range of transfer types from single to multiple data transfers  burst transfer capability  emi and power consumption minimized lmb-bus the local memory bus is a synchronous, pipelined, split bus with variable block size transfer support. all signals relate to the positive clock edge. the protocol supports 8,16,32 & 64 bits si ngle beat transactions and variable length 64 bits block transfers. key features: the lmb provides the following features:  optimized for high speed and high performance  32 bit address, 64 bit data busses  central simple per cycle arbitration  slave controlled wait state insertion  address pipelining (max. depth - 2)  split transactions  variable block length - 2, 4 or 8 beats of 64 bit data
tc1920 data sheet 22 v 1.3, 2003-10 preliminary on-chip debug system (ocds) the tc1920 architecture is supporting ocds level 1 and 2. level run time control system access via basic pc trace jtag trace bus 1yes yesno no 2 yes yes yes yes table 2 core-related and system control modules module address range i/o lines interrupt nodes tricore cpu slave registers (cps) f7e0 ff00 h - f7e0 ffff h - cpu_src0..3 cpu_srcsb memory management 1) unit (mmu) f7e1 8000 h - f7e1 80ff h -- segment protection registers 1) f7e1 c000 h - f7e1 c0ff h -- core debug 1) (core ocds) f7e1 fd00 h - f7e1 fdff h -- tricore cpu 1) sfr, gpr f7e1 fe00 h - f7e1 ffff h -- program memory unit 2) (pmu) f87f fd00 h - f87f fdff h -- data memory unit 2) (dmu) f87f fc00 h - f87f fcff h -- peripheral control processor (pcp) f000 3f00 h - f000 3fff h - pcp_src0..11 external bus unit (ebu) f800 0000 h - f800 03ff h ad[31:0], a[23:0], 27 control lines - system control unit (scu) f000 0000 h - f000 00ff h 4 xtal, porst , hrst , 8 exin, nmi , 4 test, clkout, bypass exi_src0..4 nmi 3) fpi bus control unit (bcu) f000 0200 h - f000 02ff h - bcu_src
tc1920 preliminary data sheet 23 v 1.3, 2003-10 on-chip peripheral units the tc1920 offers several on-chip peripheral units such as serial controllers, timer units, ad converter and codec interface. within the tc1920 all these peripheral units are connected to the tricore cpu/system via t he fpi (flexible peripher al interconnect) bus. several io lines on the tc1920 ports are reserved for these peripheral units to communicate with the external world. peripheral units of the tc1920:  three asynchronous/synchronous serial channels with baudrate generator, parity, framing and overrun error detecti on, irda mode, fifo buffers.  one high speed synchronous serial channels with programmable data length and shift direction  twincan module with two interconnected can nodes for high efficiency data handling via fifo buffering and gateway data transfer  serial data link module compliant to sae class b j1850 specification  iic module with connection to 2 external busses  2 multi-functional general purpose timer units with three 32-bit timer/counter  one analog-to-digital converter units with 8-bit, 10-bit, or 12-bit resolution and 6 analog inputs  dual channel codec interface  gpio blocks lmb bus control unit (lcu) f87f fe00 h - f87f feff h - lcu_src lmb to fpi bus bridge (lfi) f87f ff00 h - f87f ffff h -- port control (ports 0, 1, 2, 3, 5) f000 2800 h - f000 2cff h p0 (7), p1(7), p2(15), p3(15), p5(15) - debug support (jtag, ocds) f000 0400 h - f000 04ff h trst , tck, tdi, tdo, tms, ocdse , brkin , brkout, 16 trace outputs - 1) this address range is also accessed via the cps by the fpi bus. 2) this address range is accessed via the lmb. 3) the nmi is directly connected to the core (no src) and always acts on the highest priority. it is used as highest priority interrupt for the nmi input, the watchdog, the pll and for wake-up via the rtc or via the exix inputs. table 2 core-related and system control modules (cont?d) module address range i/o lines interrupt nodes
tc1920 data sheet 24 v 1.3, 2003-10 preliminary table 3 peripheral modules module address range i/o lines interrupt nodes asynchronous serial channel 0 (asc0) f000 0a00 h - f000 0aff h rdx0, tdx0 asc0_tsrc asc0_rsrc asc0_esrc asc0_tbsrc asynchronous serial channel 1 (asc1) f000 0b00 h - f000 0bff h rdx1, tdx1 asc1_tsrc asc1_rsrc asc1_esrc asc1_tbsrc asynchronous serial channel 2 (asc2) f000 0c00 h - f000 0cff h rdx2, tdx2 asc2_tsrc asc2_rsrc asc2_esrc asc2_tbsrc synchronous serial channel (ssc) f000 0800 h - f000 08ff h sclk, mrst, mtsr ssc_tsrc ssc_rsrc ssc_esrc inter-ic bus (iic) f000 0500 h - f000 05ff h scl[1:0], sda[1:0] iic_xp0src iic_xp1src iic_xp2src real time clock (rtc) f000 0100 h - f000 01ff h -rtc_src system timer unit (stm) f000 0300 h - f000 03ff h -- general purpose timer 0 (gptu0) f000 0700 h - f000 07ff h gptu0[7:0] gptu0_src0..7 general purpose timer 1 (gptu1) f000 0600 h - f000 06ff h gptu1[7:0] gptu1_src0..7 can (twincan) f010 0000 h - f010 0bff h rxdcan[1:0], txdcan[1:0] can_src0..7 sdlm (j1850) f000 2600 h - f000 26ff h rxj1850, txj1850 sdlm_src0..1
tc1920 preliminary data sheet 25 v 1.3, 2003-10 asynchronous/synchronous serial interfaces (asc 0/1/2) the asynchronous/synchronous serial interface asc provides serial communication between the tricore and other microcontrollers, microprocessors or external peripherals. the implementation is held parametrizable in order to allow the usage of parallel busses of different width and with different protocols. features:  full duplex asynchronous operating modes ? 8- or 9-bit data frames, lsb first ? parity bit generation/checking ? one or two stop bits ? baudrate from 3.125 mbaud to 0.74 baud (@ 50 mhz module clock) ? multiprocessor mode for automatic address/data byte detection ? loop-back capability  half-duplex 8-bit synchronous operating mode ? baudrate from 6.25 mbaud to 637 baud (@ 50 mhz module clock)  double buffered transmitter/receiver  interrupt generation ? on a transmitter buffer empty condition ? on a transmit last bit of a frame condition ? on a receiver buffer full condition ? on an error condition (frame, parity, overrun error)  support for irda  automatic baudrate detection  8 byte fifo speech interface (codec) f000 2400 h - f000 24ff h 2*2 analog in, 2*2 analog out, cext, codec_dis codec_src0..5 analog to digital converter (adc) f000 2200 h - f000 23ff h ain[5:0] = p4, ademux[2:0], adextin adc_src0..3 table 3 peripheral modules (cont?d) module address range i/o lines interrupt nodes
tc1920 data sheet 26 v 1.3, 2003-10 preliminary figure 7 asc interface diagram mca05253 clock control address decoder interrupt control f hw_clk asc module (kernel) port control rxd txd rxd txd tir tbir rir eir abstir abdetir
tc1920 preliminary data sheet 27 v 1.3, 2003-10 high-speed synchronous serial interface (ssc) the high speed synchronous serial interface ssc provides serial communication between microcontrollers, microprocessors or external peripherals. the ssc supports full-duplex and half-duplex synchronous communication up to 25 mbaud (@ 50 mhz module clock). the serial clock signal can be generated by the ssc itself (master mode) or be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi-compatible devices. transmission and reception of data are double-buffered. a 16-bit baud rate generator provides the ssc with a separate serial clock signal. features:  master and slave mode operation ? full-duplex or half-duplex operation  flexible data format ? programmable number of data bits : 2 to 16 bit ? programmable shift direction : lsb or msb shift first ? programmable clock polarity : idle low or high state for the shift clock ? programmable clock/data phase : data shift with leading or trailing edge of sclk  maximum baudrates: 25 mbaud in master, 12.5 in slave mode (@ 50 mhz module clock) interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baudrate, transmit error)  three pin interface figure 8 ssc interface diagram mcb04505_mod clock control address decoder interrupt control f hw_clk ssc module (kernel) port control mrst rxd txd master rxd txd slave slave master sclk mtsr sclk eir rir tir
tc1920 data sheet 28 v 1.3, 2003-10 preliminary inter-ic interface (iic) iic supports a certain protocol to allow devices to communicate directly with each other via two wires. one line is responsible for clock transfer and synchronization (scl), the other is responsible for the data transfer (sda). the on-chip iic bus module connects the pla tform buses to other external controllers and/or peripherals via the two-line serial iic interface. the iic bus module provides communication at data rates of up to 400 kbit/s and features 7-bit addressing as well as 10-bit addressing. this module is fully compatible to the iic bus protocol. figure 9 iic bus line connections the module can operate in three different modes: master mode , where the iic controls the bus trans actions and provides the clock signal. slave mode , where an external master controls the bus and provides the clock signal. multimaster mode , where several masters can be connected to the bus, i.e. the iic can be master or slave. the module unloads the cpu of low level tasks like:  (de)serialization of bus data.  generation of start and stop conditions.  monitoring the bus lines in slave mode.  evaluation of the device address in slave mode.  bus access arbitration in multimaster mode. iic features:  extended buffer allows up to 4 send/receive data bytes to be stored.  selectable baud rate generation.  support of standard 100 kbaud and extended 400 kbaud data rates.  operation in 7-bit addressing mode or 10-bit addressing mode.  flexible control via interrupt service routines or by polling.  dynamic access to up to 2 physical iic busses. iic kernel generic data line generic clock line sda0 sda1 scl0 scl1 iic m odule
tc1920 preliminary data sheet 29 v 1.3, 2003-10 can interface (twincan) figure 10 shows a global view of the func tional blocks of the twincan module. figure 10 general block diagram of the twincan interfaces twincan features:  can functionality according to can specification v2.0 b active.  dedicated control registers are provided for each can node.  a data transfer rate up to 1mbaud is supported.  flexible and powerful message transfer control and error handling capabilities are implemented.  full-can functionality: 32 message objects can be individually ? assigned to one of the two can nodes, ? configured as transmit or receive object, ? participate in a 2,4,8,16 or 32 message buffer with fifo algorithm, ? setup to handle frames with 11 bit or 29 bit identifiers, ? provided with programmable acceptance mask register for filtering, ? monitored via a frame counter, ? configured to remote monitoring mode.  up to eight individually programmable interrupt nodes can be used.  can analyzer mode for bus monitoring is implemented. the twincan module has four io lines. the twincan module is further supplied by a clock control, interrupt control, address decoding, and port control logic. mcb04515 clock control address decoder interrupt control f can twincan module kernel port control can node a can node b twincan control message object buffer txdca rxdca txdcb rxdcb
tc1920 data sheet 30 v 1.3, 2003-10 preliminary the can module contains two full-can nodes operating independently or exchanging data and remote frames via a gateway function. transmission and reception of can frames is handled in accordance to can specification v2.0 part b (active). each of the two full-can nodes can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. both can nodes share the twincan module?s resources in order to optimize the can bus traffic handling and to minimize the cpu load. the flexible combination of full- functionality and fifo architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. im proved can bus monitoring functionality as well as the increased number of mess age objects permit precise and comfortable can bus traffic handling. depending on the application, each of the 32 message objects can be individually assigned to one of the two can nodes. gateway functionality allows automatic data exchange between two separate can bus systems, which reduces cpu load and improves the real time behavior of the entire system. the bit timings for both can nodes are derived from the peripheral clock (f can ) and are programmable up to a data rate of 1 mbaud. a pair of receive and transmit pins connect each can node to a bus transceiver.
tc1920 preliminary data sheet 31 v 1.3, 2003-10 serial data link module (j1850) figure 11 shows a global view of the func tional blocks of the j1850 interface. figure 11 general block diagram of the sdlm interface the j1850 module communicates with the ex ternal world via tw o i/o lines, the j1850 bus. the rxd line is the receive data input signal and txd is the transmit data output signal. the serial data link module provides serial communication to a j1850 based serial bus. j1850 bus transceivers have to be implemented externally in a system. the j1850 module is conform to the sae class b j1850 specification and compatible to class 2 protocol. general sdlm features:  compliant to sae class b j1850 specification  full support of gm class 2 protocol  variable pulse width (vpw) format with 10.4 kbaud  high speed receive/transmit 4x mode with 41.6 kbaud  digital noise filter  power save mode and automatic wake up upon bus activity  support of single byte headers or consolidated headers  crc generation & check  support of block mode for receive and transmit data link operation features:  11 bytes transmit buffer  double buffered 11 bytes receive buffer  support of in-frame response (ifr) types 1,2,3  advanced interrupt handling for rx, tx and error conditions  all interrupt sources can be enabled/disabled individually  support of automatic ifr for types 1, 2 for three byte consolidated headers mcb04550 clock control address decoder interrupt control f sdlm sdlm module (kernel) port control rxj1850 rxd txd txj1850
tc1920 data sheet 32 v 1.3, 2003-10 preliminary timer units (gptu 0/1) figure 12 shows a global view of all functional blocks of one gptu module. figure 12 general block diagram of the gptu interface the gptu consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. the gptu communicates with the external world via eight inputs and eight outputs. the three timers of the gptu module t0, t1, and t2, can operate independently from each other, or can be combined: general features:  all timers are 32-bit precision timers with a maximum input frequency of f gptu /2.  events generated in t0 or t1 can be used to trigger actions in t2  timer overflow or underflow in t2 can be used to clock either t0 or t1  t0 and t1 can be concatenated to form one 64-bit timer features of t0 and t1:  each timer has a dedicated 32-bit reload register with automatic reload on overflow  timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers  overflow signals can be selected to generate service requests, pin output signals, and t2 trigger events  two input pins can determine a count option mcb05052_modified clock control address decoder interrupt control sr1 sr2 f gptu sr3 sr0 gptu module (kernel) port control p0.1 / g pt1 sr7 sr6 sr5 sr4 in 1 in 2 in 3 in 0 in 7 in 6 in 5 in 4 out0 out1 out2 out3 out4 out5 out6 out7 io 1 io 7 io 0 p0.0 / g pt0 io 2 p0.2 / g pt2 io 3 p0.3 / g pt3 p0.4 / g pt4 io 4 io 5 p0.5 / g pt5 io 6 p0.6 / g pt6 p0.7 / g p t7
tc1920 preliminary data sheet 33 v 1.3, 2003-10 features of t2:  optionally count up or down  operating modes: ?timer ? counter ? incremental interface mode  options: ? external start/stop, one-shot operat ion, timer clear on external event ? count direction control through software or an external event ? two 32-bit reload/capture registers  reload modes: ? reload on overflow or underflow ? reload on external event: positive transition, negative transition, or both transitions  capture modes: ? capture on external event: positive transition, negative transition, or both transitions ? capture and clear timer on external event: positive transition, negative transition, or both transitions  can be split into two 16-bit counter/timers  timer count, reload, capture, and trigger functions can be assigned to input pins. t0 and t1 overflow events can also be assigned to these functions.  overflow and underflow signals can be used to trigger t0 and/or t1 and to toggle output pins  t2 events are freely assignable to the service request nodes.
tc1920 data sheet 34 v 1.3, 2003-10 preliminary analog to digital converter (adc) figure 13 shows a global view of the adc module kernel with the module specific interface connections. figure 13 general block diagram of the adc module the on-chip adc module of the tc1920 is an analog to digital converter with 8-bit, 10- bit or 12-bit resolution including sample & hold functionality. the a/d converter operates by the method of the successive approximation. a multiplexer selects between up to 6 analog input channels. conversion requests are generated either under software control or by hardware. an automatic self-ca libration adjusts the adc module to changing temperatures or process variations. tc1920_adc_blockdiagram clock control address decoder interrupt control sr1 sr2 f adc sr3 sr0 adc module kernel emux0 emux1 emux2 ain0 ain1 ain5 v agnd v ssa v dda v ddm v aref v ssm asgt etr, egt qtr, qgt ttr, tgt interrupt inputs exi0in exi7in adextin port control sw0tr=0 sw0gt=1
tc1920 preliminary data sheet 35 v 1.3, 2003-10 features: the following functionality has been implemented in the on chip adc module to fulfill the enhanced requirements of embedded control applications:  8-bit, 10-bit, 12-bit a/d conversion  successive approximation conversion method  total unadjusted error (tue) of 2 lsb @ 10-bit resolution  integrated sample and hold functionality  6 analog input channels  dedicated control and status registers for each analog channel  flexible conversion request mechanisms  selectable reference voltages for each channel  programmable sample and conversion timing schemes  limit checking  flexible adc module service request control unit  automatic control of external analog multiplexer  equidistant samples initiated by timer  external trigger inputs for conversion requests  power reduction and clock control feature real time clock unit rtc the real time clock (rtc) module is basically an independent timer chain and counts clock ticks. the base frequency of the rt c can be programmed via a reload counter. the rtc can work fully asynchronous to the system frequency and is optimized on low power consumption. features: the rtc serves different purposes:  absolute system clock to dete rmine the current time and date  cyclic time based interrupt  alarm interrupt for wake up on a defined time  48-bit timer for long term measurements
tc1920 data sheet 36 v 1.3, 2003-10 preliminary codec interface the speech a/d and d/a converters (c alled codec) is designed for telephone and speech recognition quality. they can be us ed for microphone / earpiece applications. the tc1920 configuration implements a dual channel speech codec connected to the fpi bus. figure 14 general codec overview general purpose i/os (gpio)  push/pull output drivers  3.3 volt operation for gpio  programmable pull-up/-down devices at all pins  optional open drain output mode clock control address decoder interrupt control sr1 sr2 f per sr3 sr0 codec module kernel v dd cod0 clock disable external clock input ai0+ ai0- ao0+ ao0- codec_dis cext sr4 sr5 v ss cod0 v dd cod1 v ss cod1 v ref cod v gnd cod ch0 non-inv. input ch0 inv. input ch0 non-inv. output ch0 inv. output ai1+ ai1- ao1+ ao1- ch1 non-inv. input ch1 inv. input ch1 non-inv. output ch1 inv. output mute0 mute1 mute channel 0 mute channel 1 iis si g nals codec bypass 5
tc1920 preliminary data sheet 37 v 1.3, 2003-10 power supply figure 15 shows the tc1920 power supply concep t, where certain logic modules are individually supplied with power. in this way, the noise margin is improved in the especially sensitive modules, like the a/d converter and the codec. figure 15 tc1920 power supply concept x y v dda v ssa codec 0 (analog) codec 1 (analog) battery backed stand- by sram adc (analog) pll (analog) all digital core components main osc v dda v ssa v dda v ssa v dda v ssa v dda v ssa v dd v ss v dd v ss v ddp v ssp v ddp v ssp rtc osc v dda v ssa v dd_sb v ddr v ss
tc1920 data sheet 38 v 1.3, 2003-10 preliminary power-up sequence during power-up reset pin porst has to be held active until both power supply voltages have reached at least their minimum values. during the power-up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the core v dd power supply reaches its operating value first, and then the gpio v ddp power supply. during the rising time of the core voltage it must be ensured that 0< v dd -v ddp <0.5 v. during power-down, the core and gpio power supplies v dd and v ddp respectively, have to be switched off until all capacitances are discharged to zero, before the next power-up. note: the states of the pins are undefined when only the port voltage v ddp is on.
tc1920 preliminary data sheet 39 v 1.3, 2003-10 id register table table 4 list of tc1920 id registers short name description address value scu_id scu identification register f000 0008 h 0019 c002 h manid manufacturer identification register f000 0070 h 0000 1820 h chipid chip identification register f000 0074 h 0000 8902 h rtid redesign tracing identification register f000 0078 h 0000 0000 h rtc_id rtc module identification register f000 0108 h 0000 5a04 h bcu_id bcu identification register f000 0208 h 0000 6a06 h stm_id system timer module identification register f000 0308 h 0000 c002 h jdp_id jtag/ocds module identification register f000 0408 h 0000 6305 h iic_id iic module identification register f000 0508 h 0000 4604 h gptu0_id gptu module identification register f000 0708 h 0001 c002 h gptu1_id gptu module identification register f000 0608 h 0001 c002 h ssc_id ssc module identification register f000 0808 h 0000 4503 h asc0_id asc module identification register f000 0a08 h 0000 44e1 h asc1_id asc module identification register f000 0b08 h 0000 44e1 h asc2_id asc module identification register f000 0c08 h 0000 44e1 h adc_id adc module identification register f000 2208 h 0000 3104 h codec_id codec identification register f000 2408 h 001c c002 h sdlm_id sdlm module identification register f000 2608 h 0000 4204 h pcp_id pcp module identification register f000 3f08 h 0020 c003 h can_id can module identification register f010 0008 h 0000 4110 h cps_id cpu module identification register f7e0 fe08 h 0015 c004 h mmu_id mmu identification register f7e1 8008 h 0009 c002 h cpu_id cpu identification register f7e1 fe18 h 000a c003 h ebu_id ebu_lmb identification register f800 0008 h 0014 c003 h dmu_id dmu identification register f87f fc08 h 0008 c002 h pmu_id pmu module identification register f87f fd08 h 000b c002 h lcu_id lcu identification register f87f fe08 h 000f c003 h lfi_id lfi identification register f87f ff08 h 000c c003 h
tc1920 data sheet 40 v 1.3, 2003-10 preliminary electrical characteristics parameter interpretation the parameters listed in the following partly represent the characteristics of the tc1920 and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ?symbol?: cc ( c ontroller c haracteristics): the logic of the tc1920 will provide signals with the respective characteristics. sr ( s ystem r equirement): the external system must provide signals with the respective characteristics to the tc1920.
tc1920 preliminary data sheet 41 v 1.3, 2003-10 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specific ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. parameter symbol limit values unit notes min. max. ambient temperature t a -40 85 c under bias storage temperature t st -65 150 c junction temperature t j ? 125 c under bias voltage on i/o supply pins with respect to ground ( v ss ) v ddp -0.5 4.2 v voltage on core supply pins with respect to ground ( v ss ) v dd -0.3 2.1 v voltage on pll supply pins with respect to ground ( v ss ) v ddpll -0.3 2.1 v pll voltage between oscillator supply pins and ground ( v ss ). v ddosc -0.3 2.1 v voltage on any pin with respect to ground ( v ss ) v in -0.5 4.2 v input current on any pin during overload condition i ov -10 10 ma absolute sum of all input currents at overload condition i ov ? |100| ma power dissipation p diss ?1.4w
tc1920 data sheet 42 v 1.3, 2003-10 preliminary package parameters (p-lbga-260) operating conditions the following operating conditions must not be exceeded in order to ensure correct operation of the tc1920. all parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. parameter symbol limit values unit notes min. max. power dissipation p diss ?1.4w? thermal resistance r tha ? 27.8 k/w chip to ambient parameter symbol limit values unit notes min. max. supply voltage v ddp 3.0 3.6 1) 1) voltage overshoot to 4 v is permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h v i/o supply v dd 1.71 1.89 2) 2) voltage overshoot to 2 v is permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h v core supply v ddpll 1.71 1.89 v pll supply v ddosc 1.71 1.89 v oscillator supply ground voltage v ss 0v input current on any pin during overload condition i ov -5 5 ma v ov > v ddp + 0.3v v ov < v ss - 0.3v absolute sum of all input currents at overload condition | i ov | ?|50|ma ambient temperature under bias t a -40 85 c cpu clock f cpu ?100mhz external load capacitance c l ?50pf
tc1920 preliminary data sheet 43 v 1.3, 2003-10 dc characteristics gpio pins parameter symbol limit values unit test conditions min. max. output low voltage (strong driver) v ol -1 0.4 vi ol = 10 ma i ol = 2.5 ma output high voltage (strong driver) v oh 2.4 - v i oh = - 2.5 ma output low voltage (medium driver) 1) 1) not subject to production test, veri fied by design/characterization. v ol -0.4vi ol = 1 ma output high voltage (medium driver) 1) v oh 2.4 - v i oh = - 1 ma output low voltage (weak driver) 1) v ol -0.4vi ol = 100 a output high voltage (weak driver) 1) v oh 2.4 - v i oh = - 100 a input low voltage v il -0.3 0.8 v lvttl input high voltage v ih 2.0 v ddp +0.3 or 3.7v v whatever is lower input leakage current i oz1 - 500 na 0v< v in < v ddp pull-up current 2) 2) the maximum current that may be drawn while the respective signal line remains inactive. |i puh | - 1 a v out = 2.0v pull-up current 3) 3) the minimum current that must be drawn in order to drive the respective signal line active. |i pul | 20 - a v out = 0.8v pull-down current |i pdl | - 0.8 a v out = 0.8v pull-down current |i pdh | 20 - a v out = 2.0v pin capacitance 1) c io - 10 pf f = 1mhz @ t a = 25 o c
tc1920 data sheet 44 v 1.3, 2003-10 preliminary nmi pin nmi pin is an input pin with different pull-up characteristics than other pins. the related characteristics are given in the following table note: nmi pin does not have a pull-down device. oscillator pins parameter symbol limit values unit test conditions min. max. max. current allowed through the pull-up device while pin (input) voltage remains still at the high level |i puh | -4uav out =2.0v min. current needed through the pull-up device so that pin voltage is driven to the low level. |i pul | 100 - ua v out =0.8v parameter symbol limit values unit test conditions min. max. input leakage current (analog input) at xtal1 1) 1) only applicable in deep sleep mode i oz1 cc - 200 na 0v< v in < v ddp input low voltage xtal1 v ilx sr -0.3 v- input high voltage xtal1 2) 2) not subject to production test, veri fied by design/characterization. v ihx sr 0.8 v dd -0.3 v dd -0.35 v dd -0.4 v dd -0.43 vf osc =4mhz f osc =8mhz f osc =12mhz f osc =16mhz xtal1 input current i ix1 cc - 20 a 0v < v in < v dd xtal3 input current 2) i ix3 cc - 0.5 a 0v < v in < v dd
tc1920 preliminary data sheet 45 v 1.3, 2003-10 iic pins each iic pin is an open drain output pin with different characteristics than other pins. the related characteristics are given in the following table note: no 5 v iic interface is supported wit h these pads. only voltages lower than 3.60 v must be applied to these pads. note: iic pins have no pull-up and pull-down devices. parameter symbol limit values unit test conditions min. max. output low voltage v ol cc -0.4 0.6 v3 ma 6 ma input high voltage 1) v ih sr 0.7v ddp 3.6 v - input low voltage 1) v il sr -0.3 0.3v ddp v- input leakage current i oz2 cc - + - 500 na pin capacitance 1) 1) not subject to production test, veri fied by design/characterization. c io cc - 10 pf f=1mhz@ t a =25 o c
tc1920 data sheet 46 v 1.3, 2003-10 preliminary adc analog i/o dc characteristics parameter symbol limit values unit test conditions min. typ. max. core supply voltage v dd sr 1.71 1.8 1.89 v - analog supply voltage v dda sr 3.0 3.3 3.6 v - analog supply ground v ssa sr -0.1 0.0 +0.1 v - reference voltage 3) v aref 1.5 - v dda + 0.05 v- reference ground v agnd v ssa - 0.05 v ssa v ssa + 0.05 v- analog input voltage v a v agnd ? v aref v- internal a/d converter clock f ana 0.5 ? 3.5 mhz - input leakage current (analog input) i oz1 cc - 200 na 0v< v in < v dda input leakage current ( v agnd , v aref ) i oz2 cc - 500 na 0v< v in < v dda overload current i aov sr -2 +5 ma 1) 5) overload coupling factor 2) k a - 1.0x10 -4 1.5x10 -3 -i aov >0 3) i aov <0 sample time t s cc 4*(chcon n .stc+2)*t bc for channel n conversion time 3) t bc =1/f bc, t div =1/f div, see figure 17 . t c cc t s + 40*t bc + 2*t div for 8- bit conversion t s + 48*t bc + 2*t div for 10- bit conversion t s + 56*t bc + 2*t div for 12- bit conversion
tc1920 preliminary data sheet 47 v 1.3, 2003-10 total unadjusted error 4) tue cc 1 lsb for 8- bit conversion 2 lsb for 10- bit conversion 6 lsb 5) for 12- bit conversion on resistance of the transmission gates in the analog voltage path 7) r ain cc 1900 ohm resistance of the reference voltage path 7) r ref cc 2000 ohm switched capacitance at the analog voltage input. 7) c ainsw cc 10 pf total capacitance at analog voltage input 6) c aintot cc -15- pf switched capacitance at the positive reference voltage input. 7) c arefsw cc 15 pf 1) analog overload conditions during operation occur if the voltage on the respective adc pin exceeds the specified operating range (i.e. v aov > v ddp +0.3v or v aov < v ssp - 0.3v ) or a short circuit condition occurs on the respective adc pin. the absolute sum of input leakage and i aov currents on all port pins must not exceed 10 ma at any time. the supply voltage ( v dd , v ddp and v ss , v ssp ) must remain within the specified limits. under short-circuit conditions the corresponding pin is not ready for use. 2) the overload coupling factor ( k a ) defines the worst case relation of an overload condition ( i ov ) at one pin to the resulting total leakage current ( i leaktot ) into an adjacent pin: | i leaktot | = k a | i ov | + i oz1v thus under overload conditions an additional error leakage voltage ( v ael ) will be induced onto an adjacent analog input pin due to the resistance of the analog input source ( r ain ). that means v ael = r ain | i leaktot |. please see also the analog/digital converter specification, chapter ?error through overload conditions?, for further explanations. 3) the nominal conversion time is valid for v aref >3.0. for v aref <3.0, it is approximately double. 4) at v aref =+3.3v and v agnd in the specified range. for v aref <3.3v, tue rise and is to be multiplied with a factor of 3.3/vref. for v agnd outside the specified range, tue is not guaranteed. 5) tested in production on request. standard production test is 10-bit tue test. 6) not subject to production test, veri fied by design/characterization. 7) simulation values. parameter symbol limit values unit test conditions min. typ. max.
tc1920 data sheet 48 v 1.3, 2003-10 preliminary figure 16 equivalent circuitry of an analog input figure 17 adc clock circuit mcs04879 r ain, source = v ain c ain, block r ain, on c aintot - c ainsw c ainsw a/d converter mca04657_mod programmable clock divider (1:1) to (1:256) f bc f div f adc f ana sample time t s con.pcd con.ctc chconn.stc f timer control/status logic interrupt logic external trigger logic external multiplexer logic request generation logic a/d converter module arbiter (1:20) control unit (tim er) 1:4 programmable counter peripheral clock divider (1:1) to (1:8)
tc1920 preliminary data sheet 49 v 1.3, 2003-10 codec electrical characteristics parameter symbol limit values unit test conditions min. typ. max. digital supply voltage v dd 1.71 1.8 1.89 v analog supply voltage v dda 3.0 3.3 3.6 v analog supply ground v ssa -0.1 0.0 +0.1 v external reference voltage v aref 1) 1) reference voltage outside the nominal range causes reduced dynamic range, decreased distortion/clipping margins, increased/decreased gain. 1.14 1.2 +1.26 2) 2) v ssa =v agnd =0v v analog reference ground v agnd v ssa - 0.05 v ssa v ssa + 0.05 v analog input voltage (rms) v ain 0.775 v rms 3) 3) please take the gain settings of the analog preamplifier into account, therefore v imaxreal =v imax /gain analog output voltage (rms) v aout 0.775 v rms input resistace of the analog inputs 4) 4) simulation value. ra - 30 - kohm differential input, gain: -12,-6, 0 db - 15 - kohm single-ended input, gain: -12,-6, 0 db - 60 - kohm differential input, gain: 6 to 30 db - 30 - kohm single-ended input, gain: 6 to 30 db internal reference voltage vref (bandgap voltage) 5) 5) for external usage only, bandgap reference voltage is strongly dependent on the external load (<500 mohm). in this case, high impedance buffer must be used. v bgp 1.1 1.2 1.3 v agccr. bgpsel[1,0] =00
tc1920 data sheet 50 v 1.3, 2003-10 preliminary codec adc and dac path characteristics note: numbers without units in the test conditions column are relative frequency values to the chosen sampling frequency. e.g. 0.425 equals 3.4 khz @ 8 khz sampling frequency. parameters min. typ. max. unit test conditions 1) 1) values given in this table are valid for all sampling frequencies. attenuation distortion (ref. freq. 1014 hz) (ref. level 0dbm0) 2) 2) 0dbm0 is equivalent to -12dbm is equal to 194.7 mv rms. 0 -0.25 -0.25 -0.25 0 0.25 0.45 db db db db db < 0.025 0.025-0.0375 0.0375-0.3 0.3-0.425 > 0.425 signal to total distor- tion -55 -45 db at 0dbm0 gain tracking (ref. freq. 1014 hz) (ref. level 0dbm0) 2) -0.3 -0.6 -1.6 0.3 0.6 1.6 db db db +3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 idle channel noise -80 -75 dbm 0 receive &transmit cross talk -80 -75 db harmonic distortion -60 -50 db at 0dbm0 gain (ref. freq. 1014 hz) (ref. level 0dbm0) 2) -0.8 0 0.8 db receive &transmit power supply rejection ratio (psrr) --60 -40 -35 -35 db db receive (0.0375-0.425) 3) transmit (0.0375-0.425) 3) 3) supply ripple 70 mv.
tc1920 preliminary data sheet 51 v 1.3, 2003-10 power supply current ac characteristics operating conditions apply. output rise/fall times gpio pins rise/fall time measurements are made between 10% and 90%. the following table is valid for the gpio pins pad drivers. output pad characteristics are controllable via drvctrx registers. parameter symbol limit values unit test conditions typ. 1) 1) typical values are measured at 25c, cpu clock at 100mhz and nominal supply voltage, i.e. 3.3v for v ddp and 1.8v for v dd , v ddpll , v ddosc max. active mode supply current 2) 3) 2) porst =v ih 3) the typical power consumption values in active mode are measured while running a typical application pattern. the power consumption of modules can increase or decrease using different application programs. the pll is bypassed and powered down during this measurement. i dd 260 ? ma sum of all i dd . idle mode supply current 4) 4) cpu is in idle state, input clock to all peripherals are enabled. i id 170 ? ma at 1.8v core supply deep sleep mode supply current i dds 0.25 ? ma at 1.8v core supply pad modus rise / fall time symbol limit values temp comp unit test conditions min. max. strong driver  sharp edge  medium edge 1)  soft edge 1) 1) not subject to production test, veri fied by design/characterization. sf sm ss - - - 3 6 12 yes yes yes ns ns ns @50pf @50pf @50pf
tc1920 data sheet 52 v 1.3, 2003-10 preliminary timing characteristics (operating conditions apply) note: timing parameters are not subject to production test, they are verified by design/ characterization. figure 18 input/output waveforms for ac tests - for gpio, dedicated and ebu pins external oscillator at xtal1 timing requirements (operating conditions apply) parameter symbol limits unit min. max. main oscillator xtal frequency 1) with/without pll f osc sr 4 16 mhz frequency of an external oscillator driving at xtal1 2) with pll 3) without pll 4) f oscdd sr 4 - 25 25 mhz input clock high time t 1 sr 16 ? ns input clock low time t 2 sr 16 ? ns input clock rise time t 3 sr ? 7ns input clock fall time t 4 sr ? 7ns mct04880 2.4v 0.4v 2.0v 0.8v 2.0v 0.8v test p oints ac inputs during testing are driven at 2.4v for a logic ?1? and 0.4v for a logic ?0?. timing measurements are made at v ihmin for a logic ?1? and v ilmax for a logic ?0?.
tc1920 preliminary data sheet 53 v 1.3, 2003-10 figure 19 external clock at xtal1 requirements note: v ddosc , v ihx and v ihl are defined in the oscillator pins dc characteristics chapter. note: it is strongly recommended to meas ure the oscillation allowance (negative resistance) in the final target system (l ayout) to determine the optimal parameters for the oscillator operation. please refer to the limits specified by the crystal supplier. 1) oscillator bypass pin p3.11 latch-in value high. internal oscillator provides the input clock signal. 2) oscillator bypass pin p3.11 latch-in value low. internal oscillator disabled. external oscillator provides the input clock signal. 3) internal pll provides the system clock. bypass pin latch-in value low. pll prescaler value p=1. 4) internal pll bypassed. bypass pin latch-in value high. external oscillator provides the system clock directly. when adc and codec modules are active their frequency limitations must be taken into consideration, together with lmb/fpi bus frequency ratio. otherwise, minimum frequency in this mode can go as low as zero. mct04882 0.5 v ddosc input clock at xtal1 t osc t 1 t 2 v il x v ih x t 4 t 3
tc1920 data sheet 54 v 1.3, 2003-10 preliminary cpu clock timing (operating conditions apply; c l = 50 pf) figure 20 clkout timing parameter symbol limits unit min. max. clkout period t clkout cc 10 ? ns clkout high time t 1 cc 4 ? ns clkout low time t 2 cc 4 ? ns clkout rise time t 3 cc ? 3ns clkout fall time t 4 cc ? 3ns 0.9 v dd mct04883 0.5 v dd clkout t cpuclk t 1 t 2 0.1 v dd t 4 t 3
tc1920 preliminary data sheet 55 v 1.3, 2003-10 pll parameters note: when tc1920 starts-up with the pll not bypassed, first user instructions are executed with the frequency defined by the vco free-running frequency ( f pllbase ) and by the reset value of the pll_clc register (the k-divider and vcosel bitfields). it is software responsibility to initialize its own appropriate values in the bitfields in this register, before giving the command for the vco to lock to the input frequency. for more information, see the users manual, system units, system control unit chapter. parameter symbol limit values 1) 1) not subject to production test, veri fied by design/characterization. unit min. max. accumulated jitter d n see figure 21 ? vco frequency range f vco 100 150 2) 2) @ vcosel = ?00? mhz 150 200 3) 3) @ vcosel = ?01? mhz 200 250 4) 4) @ vcosel = ?10? mhz 250 300 5) 5) @ vcosel = ?11? mhz pll base frequency f pllbase 20 80 2) mhz 20 130 3) mhz 20 180 4) mhz 20 230 5) mhz pll lock-in time t l ? 200 s
tc1920 data sheet 56 v 1.3, 2003-10 preliminary figure 21 approximated maximum accumulated pll jitter the following two formulas define the (absolute) approximate maximum value of jitter d n in [ns] dependent on the k-factor, the system clock frequency f sys in [mhz], and the number p of consecutive f sys periods. [1] [2] with rising number p of clock cycles the maximum jitter increases linearly up to a specific value of p . beyond this value of p the maximum accumulated jitter remains at a constant value. tc1920_pll_jitter 0 0.0 p ns d n 1.0 2.0 3.0 5.0 510 15 20 25 30 4.0 35 d n p k = max. jitter = number of consecutive f sys periods = k-divider of pll f sys = 100 mhz ( k = 3) f sys = 80 mhz ( k = 3) f sys = 60 mhz ( k = 5) f sys = 40 mhz ( k = 7) for p < 0.25 f sys d n [ns] = [( 735 f sys k + 0.9) p f sys 0.25 + 0.5 ] for p > d n [ns] = [ 0.25 f sys 735 f sys k + 1.4 ]
tc1920 preliminary data sheet 57 v 1.3, 2003-10 timing for ebu_lmb clock outputs (operating conditions apply; c l = 50 pf) figure 22 ebu_lmb clock output timing parameter symbol limits unit min. max. ebuclk period t 1 cc 10 ? ns ebuclk high time t 2 cc 4.5 ? ns ebuclk low time t 3 cc 3 ? ns ebuclk rise time t 4 cc ? 2.5 ns ebuclk fall time t 5 cc ? 2.5 ns bfclk0 period t 6 cc 20 ? ns bfclk0 high time t 7 cc 9 ? ns bfclk0 low time t 8 cc 9 ? ns bfclk0 rise time t 9 cc ? 3.5 ns bfclk0 fall time t 10 cc ? 2.5 ns 0.9 v dd mct04884 0.5 v dd ebuclk/ bfclk0 t 1 (t 6 ) t 2 (t 7 ) 0.1 v dd t 3 (t 8 ) t 5 (t 10 ) t 4 (t 9 )
tc1920 data sheet 58 v 1.3, 2003-10 preliminary timing for sdram access signals (operating conditions apply; c l = 50 pf) parameter symbol limits unit min. max. cke high from ebuclk t 1 cc - 7.0 ns cke low from ebuclk t 2 cc 2.0 - ns a(23:0) output valid from ebuclk t 3 cc - 7.0 ns a(23:0) output hold from ebuclk t 4 cc 2.0 - ns cs(6:0) low from ebuclk t 5 cc - 7.0 ns cs(6:0) high from ebuclk t 6 cc 2.0 - ns ras low from ebuclk t 7 cc - 7.0 ns ras high from ebuclk t 8 cc 2.0 - ns cas low from ebuclk t 9 cc - 7.0 ns cas high from ebuclk t 10 cc 2.0 - ns rd/wr low from ebuclk t 11 cc - 7.0 ns rd/wr high from ebuclk t 12 cc 2.0 - ns bc(3:0) low from ebuclk t 13 cc - 7.0 ns bc(3:0) high from ebuclk t 14 cc 2.0 - ns ad(31:0) output valid from ebuclk t 15 cc - 7.7 ns ad(31:0) output hold from ebuclk t 16 cc 2.0 - ns ad(31:0) input setup to ebuclk t 17 sr 2.0 - ns ad(31:0) input hold from ebuclk t 18 sr 4.0 - ns
tc1920 preliminary data sheet 59 v 1.3, 2003-10 figure 23 sdram access timing mct05319 column row column row data (n-1) data (0) ebuclk cke a(23:0) csx ras cas t 1 write access: t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 rd/wr bc(3:0) ad(31:0) ebuclk cke a(23:0) csx ras cas read access: t 3 t 4 t 6 t 10 rd/wr bc(3:0) ad(31:0) data (0) data (n-1) t 2 t 9 t 13 t 14 t 17 t 18
tc1920 data sheet 60 v 1.3, 2003-10 preliminary timing for burst flash access signals operating conditions apply; c l = 50 pf) parameter symbol limits unit min. max. a(23:0) output valid from bfclk0 t 1 cc ? 11.0 ns a(23:0) output hold from bfclk0 t 2 cc 0.0 ? ns cs(6:0) low from bfclk0 t 3 cc ? 9.0 ns adv low from bfclk0 t 5 cc ? 10.0 ns adv high from bfclk0 t 6 cc 3.0 ? ns baa low from bfclk0 t 7 cc ? 10.0 ns baa high from bfclk0 t 8 cc 3.0 ? ns rd low from bfclk0 t 9 cc ? 10.0 ns ad(31:0) input setup to bfclk0 t 11 sr 6.0 ? ns ad(31:0) input hold from bfclk0 t 12 sr 3.0 ? ns
tc1920 preliminary data sheet 61 v 1.3, 2003-10 figure 24 burst flash access timing (instruction read) address valid valid valid bfclk0 t 1 t 5 t 6 t 3 t 9 t 7 t 8 t 12 t 11 a[23:0] rd baa adv d[31:0] note: between the end of the address phase (adv goes high) and the beginning of the command phase (rd goes low) several cycles of command delay phase can be inserted. csx t 2 mct04889_mod_la
tc1920 data sheet 62 v 1.3, 2003-10 preliminary timing for demultiplexed access signals 1) (operating conditions apply; c l = 50 pf) 1) it is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase length according to the particular asynchronous memory/peripheral device specification. parameter symbol limits uni t min. max. ale high from ebuclk t 1 cc ? 8.0 ns ale low from ebuclk t 2 cc 2.0 ? ns a(23:0) output valid from ebuclk t 3 cc ? 8.0 ns a(23:0) output hold from ebuclk t 4 cc 2.0 ? ns cs(6:0) low from ebuclk t 5 cc ? 8.0 ns cs(6:0) high from ebuclk t 6 cc 2.0 ? ns mr/w low from ebuclk t 7 cc ? 8.0 ns mr/w high from ebuclk t 8 cc 2.0 ? ns rmw low from ebuclk t 9 cc ? 8.0 ns rmw high from ebuclk t 10 cc 1.0 ? ns rd low from ebuclk t 11 cc ? 8.0 ns rd high from ebuclk t 12 cc 0.0 ? ns rd/wr low from ebuclk t 13 cc ? 8.0 ns rd/wr high from ebuclk t 14 cc 2.0 ns cmdelay input setup to ebuclk t 15 sr 4.0 ? ns cmdelay hold from ebuclk t 16 sr 3.0 ? ns wait input setup to ebuclk t 17 sr 4.0 ? ns wait hold from ebuclk t 18 sr 3.0 ? ns bc(3:0) low from ebuclk t 19 cc ? 8.0 ns bc(3:0) high from ebuclk t 20 cc 2.0 ? ns ad(31:0) output valid from ebuclk t 21 cc ? 8.0 ns ad(31:0) output hold from ebuclk t 22 cc 0.0 ? ns ad(31:0) input setup to ebuclk t 23 sr 4.0 ? ns ad(31:0) input hold from ebuclk t 24 sr 4.0 ? ns
tc1920 preliminary data sheet 63 v 1.3, 2003-10 figure 25 demultiplexed write access address mct05320 ebuclk t 1 t 2 t 3 t 4 t 6 t 5 t 7 t 14 ale a(23:0) csx mr/w rd/wr cmdelay t 15 t 16 wait t 17 t 18 t 19 bc(3:0) t 20 t 13 t 20 t 19 data out t 21 t 22 ad(31:0)
tc1920 data sheet 64 v 1.3, 2003-10 preliminary figure 26 demultiplexed read access address mct05321 ebuclk t 1 t 2 t 3 t 4 t 6 t 5 t 8 ale a(23:0) csx mr/w rd cmdelay wait t 17 t 18 t 19 bc(3:0) t 11 t 20 t 19 data t 24 ad(31:0) rmw t 9 t 10 t 12 t 15 t 16 t 23 note: rmw signal is available only during read-modify-write access.
tc1920 preliminary data sheet 65 v 1.3, 2003-10 timing for multiplexed access signals 1) (operating conditions apply; c l = 50 pf) 1) it is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase length according to the particular asynchronous memory/peripheral device specification. parameter symbol limits unit min. max. ale high from ebuclk t 1 cc ? 8.0 ns ale low from ebuclk t 2 cc 2.0 ? ns ad(31:0) output valid from ebuclk t 3 cc ? 8.0 ns ad(31:0) output hold from ebuclk t 4 cc 0.0 ? ns ad(31:0) input setup to ebuclk t 5 sr 4.0 ? ns ad(31:0) input hold from ebuclk t 6 sr 4.0 ? ns cs(6:0) low from ebuclk t 7 cc ? 8.0 ns cs(6:0) high from ebuclk t 8 cc 1.0 ? ns mr/w low from ebuclk t 9 cc ? 8.0 ns mr/w high from ebuclk t 10 cc 2.0 ? ns rmw low from ebuclk t 11 cc ? 8.0 ns rmw high from ebuclk t 12 cc 1.0 ? ns rd/wr low from ebuclk t 13 cc ? 8.0 ns rd/wr high from ebuclk t 14 cc 2.0 ? ns rd low from ebuclk t 15 cc ? 8.0 ns rd high from ebuclk t 16 cc 0.0 ? ns cmdelay input setup to ebuclk t 17 sr 4.0 ? ns cmdelay hold from ebuclk t 18 sr 3.0 ? ns wait input setup to ebuclk t 19 sr 4.0 ? ns wait hold from ebuclk t 20 sr 3.0 ? ns bc(3:0) low from ebuclk t 21 cc ? 8.0 ns bc(3:0) high from ebuclk t 22 cc 2.0 ? ns
tc1920 data sheet 66 v 1.3, 2003-10 preliminary figure 27 multiplexed write access address mct05322 ebuclk t 1 t 2 t 3 t 4 t 8 t 7 t 9 t 14 ale ad(31:0) csx mr/w rd/wr cmdelay t 17 t 18 wait t 19 t 20 bc(3:0) t 22 t 13 t 22 t 21 data t 4 t 3 t 21
tc1920 preliminary data sheet 67 v 1.3, 2003-10 figure 28 multiplexed read access address ebuclk t 1 t 2 t 3 t 6 t 8 ale ad(31:0) csx data t 4 t 5 mct05323 t 8 t 7 t 10 csx mr/w rd cmdelay wait t 19 t 20 t 21 bc(3:0) t 15 t 22 t 21 rmw t 11 t 12 t 16 t 17 t 18 note: rmw signal is only available during read-modify-write access.
tc1920 data sheet 68 v 1.3, 2003-10 preliminary timing for external bus arbitration signals (operating conditions apply; c l = 50 pf) note: the signals hold , hlda and breq are alternate function of the cs5 , cs6 and csovl pins. parameter symbol limits unit min. max. hold input setup to ebuclk t 1 sr 6.0 ? ns hold input hold from ebuclk t 2 sr 8.0 ? ns hlda low from ebuclk t 3 cc ? 10.0 ns hlda high from ebuclk t 4 cc ? 9.0 ns hlda input setup to ebuclk t 5 sr 8.0 ? ns hlda input hold from ebuclk t 6 sr 8.0 ? ns breq low from ebuclk t 7 cc ? 10.0 ns breq high from ebuclk t 8 cc ? 9.0 ns
tc1920 preliminary data sheet 69 v 1.3, 2003-10 figure 29 external bus arbitration timing m ct05324_mod ebuclk hold hlda breq t 1 t 2 t 4 t 3 t 8 t 7 external master mode ebuclk breq hlda hold t 7 t 8 t 6 t 5 t 2 external slave mode t 1
tc1920 data sheet 70 v 1.3, 2003-10 preliminary ssc master mode timing (operating conditions apply; c l = 50 pf) figure 30 ssc master mode timing parameter symbol limit values unit min. max. sclk period t sclk cc 40 ns mtsr low/high from sclk edge t 5 cc - 2.0 ns mrst setup to sclk edge t 6 sr 15 - ns mrst hold from sclk edge t 7 sr 15 - ns 0.9 v dd mct04885mod 0.5 v dd sclk t sclk 0.1 v dd 0.9 v dd 0.5 v dd 0.1 v dd (con.po,con.ph=00 or 11) sclk (con.po,con.ph=01 or 10) t 5 state n-1 s tate n state n+1 data valid d ata valid t 6 t 7 mtsr mrst
tc1920 preliminary data sheet 71 v 1.3, 2003-10 package outlines figure 31 lbga-260 package you can find all of our packages, sorts of packing and other in our infineon internet page ?products?: http://www.infineon.com/products 
tc1920 data sheet 72 v 1.3, 2003-10 preliminary
((73))
http://www.infineon.com published by infineon technologies ag infineon goes for business excellence ?business excellence means inte lligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.? dr. ulrich schumacher


▲Up To Search▲   

 
Price & Availability of SAF-TC1920-LEBBA

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X